The present invention generally relates to memory subsystems and related components of computer systems. More particularly, this invention relates to methods and circuitry for altering and preferably optimizing the performance of a memory subsystem by generating different voltages for VDD and VDDQ inputs to memory components of the memory subsystem.
System memory has become one of the performance bottlenecks in current computer configurations. Memory signaling frequencies are doubling roughly every five years in order to keep up with the increased bandwidth requirements of modern system architectures. At the same time, the supply voltage of the memory subsystem is lowered in the process of transitioning to smaller process nodes. However, a recurrent trend in the advancement of memory technology is that by the time of introduction of a new generation of DRAM, the requirements for the new components by far exceed the original design specifications. For example, DDR2 was originally conceived to run at approximately 400 MHz, however, shortly after its introduction, 533, 667 and 800 MHz speed grades had to be added in order to compete with the phasing-out first generation of DDR memory running as fast as 600 MHz at lower latency. A similar trend is seen in the case with DDR3 that was originally designed for 800 MHz with a high end speed grade of 1066 MHz, which within less than two months of its introduction into the marketplace was scaled up to 1600 MHz, and shortly thereafter to 2000 MHz.
Frequency and latencies are strongly dependent on the supply voltage. If the supply voltage is increased, it is possible in most cases to increase the frequency headroom of the design or the actual components. Likewise, some of the internal logic portions of the DRAM components are sensitive to voltage in the same sense. In particular, the Column Address Strobe (CAS) speed is highly dependent on the core supply voltage of the memory chip. Higher supply voltages result in faster column addressing and, as a consequence, the CAS delay or latency on most DRAM ICs can be reduced if higher voltages are used.
A drawback of increasing the DRAM supply voltage is that all current DRAM implementations in standard computer systems specify a single supply voltage plane for both the core voltage (VDD) and the input/output voltage (VI/O or VDDQ) on both the motherboard and memory circuit board level, even though the two power planes are separate on all current DRAM chip levels. A memory module 10 illustrating this is schematically represented in FIG. 1, in which VDD and VDDQ input pins 18 and 20 at an edge connector 16 of the module printed circuit board (PCB) 12 are connected through conductor traces or lines 26 and 28, respectively, to a common plane 30 that supplies the same voltage to VDD and VDDQ input pins 22 and 24 of the memory components (chips) 14 of the module 10. As a consequence, increasing the core supply (VDD) voltage of the memory chips 14 will also increase the I/O (VDDQ) voltage of the memory chips 14 and the I/O voltage on the memory controller (not shown) that manages the flow of data going to and from the module 10. Increasing the I/O voltage, however, can compromise the reliability of the memory controller. The sensitivity to overvoltage and the associated reliability problems become particularly important if the memory controller is integrated into the central processor unit (CPU), as in the current models offered by Advanced Micro Devices, Inc. (AMD) and Intel Corporation.
It is, therefore, desirable to increase the memory core voltage in order to increase internal frequency overhead and to speed up access times of the address strobes, while keeping the I/O voltage levels at the standard system specification. However, it is difficult to retroactively change designs of the power planes of motherboards in order to separate supply voltages for the DRAM core and I/O circuitry. Moreover, even if split voltage planes were implemented on the motherboard level, it would be negated by the shared voltage planes of the memory printed circuit boards (PCBs).
One possible solution for the above problem is to have additional voltage regulators on the memory PCB that use the supply voltage as reference and then selectively lower the I/O voltage by a pre-defined amount. In this case it is also advantageous that the termination voltage on the motherboard remains unchanged at one-half of the original supply voltage, since it has been empirically found that increasing the termination voltage of the I/O system above the center of the voltage swing increases performance, whereas lowering the termination voltage below the midpoint of the voltage swing is generally detrimental to performance.
A potential drawback of the lowered memory VDDQ is that the memory voltage is supplied not only to the memory but also to the I/O portion of the memory controller. Lowering the I/O voltage on the memory module level will, therefore, cause a voltage gradient between the memory controller and the memory device that can affect the signaling properties as well as cause reverse current flow into the memory chips through the bus interface.
A different approach is to selectively boost VDD up to the desired levels. One limitation to overcome in this situation is that most current memory designs utilize internal voltage regulators to keep the core voltage at a predefined level that is lower than the supply voltage. Depending on the quality and nature of the voltage regulators, the boost in core supply voltage must be higher than the target core voltage. However, because VDD and VDDQ are completely separated on the IC level, no unwanted bleeding over should occur, especially since boosting the core voltage will essentially even out the preexisting gradient between the core and I/O voltages.
Modifications of the supply voltage of the memory subsystem have been proposed as solutions for facilitating the transition between memory generations. For example, U.S. Pat. No. 5,757,712 teaches the use of a diode to lower the voltage supplied to the DRAM in order to ensure the compatibility of lower voltage DRAM integrated circuits with high voltage systems. In another embodiment, this patent teaches the use of bus switches to adjust the I/O voltage swing to the requirement of the system. U.S. Pat. No. 7,127,622 teaches storing the operational voltage value of the DRAM in a non-volatile configuration memory, such as the serial presence detect ROM on a memory module, to allow the host to modify the memory supply voltage to the preferred voltage of the memory module. U.S. Published Patent Application No. 20080247220 describes an SRAM wherein the supply voltage is boosted during read operations.